Board P — Locked Spec and Net Table

The USB-PD front end as locked for the prototype build — adopted unchanged from the power-section audit, with the downstream connector pin assignment fixed and the ratings decision re-confirmed against Board L's actual load.

Board P is adopted unchanged from Board P — USB-PD Front End. This page locks it as a buildable spec: it restates the net table in the form KiCad capture will consume, fixes the JOUT1 pin assignment that Board L must mirror, and re-checks the audit's ratings conclusions against Board L's real (much smaller than worst-case) load.

Role

Negotiate a 15 V / 3 A USB-PD contract, gate it behind a load switch until the contract is live, and hand a switched 15 V rail plus two open-drain status flags to Board L. No lamp-specific behaviour lives here — it is a generic reusable sink module.

What this architecture pass changed

Nothing electrical. Three things were re-checked and confirmed, and one BOM optimisation was recommended here and has since been applied at KiCad capture:

1. Load re-check. Board P was margined against the 3.0 A contract cap. Board L actually draws ~410 mA (see Power budget). Every current-dependent number on Board P — Q1 conduction loss and JOUT1 contact loading — improves by roughly 7x against the original analysis. No electrical limit needs changing.

2. The conditioned clamp point propagates downstream. The exact D5/D10 SMAJ20A primary row gives VC max 32.4 V only at IPP 12.3 A for a 10/1000 µs waveform at 25 °C. Board L's input-facing parts were screened against that point, but both rail waveforms still require simulation and bench confirmation — see the driver input-rating decision.

3. The 5 V-only first-power-up rule is a hard bring-up gate, not advice. It is restated in Next Steps.

Net-connectivity table

Adopted verbatim from the power-section audit. Reproduced here so the architecture section is self-contained for schematic capture. Reference designators are Board P's own.

JOUT1 pin assignment (locked)

Board L's J2 must mirror this exactly. Board P uses the XFCN PZ254V-11-06P male header (C492405), and Board L uses its XFCN PM254V-11-06-H85 female mate (C2832269). The pair mates directly; it is unkeyed, so both pin-1 marks and the installed board orientation must be verified before power.

ATT is wired to a GPIO purely because it is free — Board P already routes it to the connector, and an input pin costs nothing. Firmware does not act on it in v1.

Ratings, re-confirmed at Board L's real load

The U1/Q1 transient envelope remains open in the ratings matrix. This architecture pass does not silently close them: the exact UMW Q1 limits are manufacturer-primary, but the retained STUSB Rev 8 limits are manufacturer-authored mirror evidence under the project's strict trust policy. The 32.4 V TVS value is also conditioned on 12.3 A, 10/1000 µs, and 25 °C. Nothing about a lower steady-state load proves the real clamp waveform; issue #34 keeps PD energization and a protected-chain PASS blocked pending mapping, simulation, programmed-state, as-built, and bench evidence.

What the design review changed (2026-08-01)

An independent electrical review of the captured schematics confirmed the netlist matches this page pin-for-pin, and made three changes to the gate network and programming interface, now reflected in the tables above:

1. C35 moved from gate–GND to gate–source (VBUS_IN). Referenced to ground, the soft-start cap held the gate down while VBUS moved — so Q1 conducted for ~16 ms at every plug-in (before any contract) and turned on hard, un-soft-started, at the 5 → 15 V transition. Referenced to the source, V_GS stays at 0 through both events and the τ = 6 ms soft-start happens only when VBEN asserts. Standard high-side P-FET practice; the ground-referenced version was a real bug.

2. R12 changed 56 kΩ → 150 kΩ. The old 100k/56k divider put V_GS at −12.8 V in a 20 V mis-contract — the exact scenario the NVM trap creates — over the AO3401A's ±12 V absolute maximum. The 100k/150k ratio gives −6.0 V at 15 V (R_DS(on) is specified at 65 mΩ maximum by −4.5 V, so the conservative conduction estimate remains low) and −8.0 V at 20 V.

3. U1.RESET is no longer hard-grounded. It reaches GND through R21 (10 kΩ, the same C17414 reel Board L uses) and is brought out on the previously unused J2.4, so the programming jig can hardware-reset the chip if an NVM write wedges the I2C state — a failure mode the zudo-pd NVM history makes worth one resistor.

The review also resolved this board's open question favourably — see the next section.

One number this pass could not resolve

Lessons Carried From zudo-pd states that R14 (470 Ω from VBUS_IN to pin 18) passes "15 V/470 Ω ≈ 32 mA", inside the pin's 50 mA IDISUSB rating. Read as a continuous current that would be 0.48 W — more than 7% of the whole lamp's power budget, dissipated in a 0603 resistor rated 100 mW, which cannot be right. Read as the discharge-event current (pin 18 is high-impedance in its sense role and only sinks during discharge) it is ~0 W steady state, and the 50 mA figure is exactly what an event-current rating looks like.

This pass believes the second reading is correct — IDISUSB is named for discharge, and a 100 mW resistor in ST's own reference topology would not be specified to run at 4.8x its rating. But it could not confirm it from the datasheet text available here. The power budget therefore carries it as a flagged worst case (+0.48 W), and Next Steps makes measuring R14's steady-state drop an explicit bring-up item. Either way the design fits inside 45 W with large margin, so this does not block the build — but do not size R14's package from the optimistic reading without measuring it.

Resolved (2026-08-01): the design review pulled ST DS12499 §2.2.12, which states the pin "is used to sense VBUS presence, monitor VBUS voltage, and discharge VBUS… A serial resistor connected to the pin must be used to limit the discharge current through the pin. Maximum discharge current is 50 mA." IDISUSB is a discharge-event current, the sense role is high-impedance, and ST's own reference schematic uses the same 470 Ω. The steady-state reading is ≈0 W, the 0603 package is fine, and the +0.48 W flagged worst case can come out of the power budget. The Gate-2 measurement stays as confirmation.

References

• Board P — USB-PD Front End — source of this circuit

• Worst-Case Ratings Matrix — per-part margin evidence

• Charger Compatibility — the 15 V-PDO purchase rule

• Lessons Carried From zudo-pd — CC topology, NVM trap, CPL rotation