Board P — Locked Spec and Net Table

The USB-PD front end as locked for the prototype build — adopted unchanged from the power-section audit, with the downstream connector pin assignment fixed and the ratings decision re-confirmed against Board L's actual load.

Board P is adopted unchanged from Board P — USB-PD Front End. This page locks it as a buildable spec: it restates the net table in the form KiCad capture will consume, fixes the JOUT pin assignment that Board L must mirror, and re-checks the audit's ratings conclusions against Board L's real (much smaller than worst-case) load.

Role

Negotiate a 15 V / 3 A USB-PD contract, gate it behind a load switch until the contract is live, and hand a switched 15 V rail plus two open-drain status flags to Board L. No lamp-specific behaviour lives here — it is a generic reusable sink module.

What this architecture pass changed

Nothing electrical. Three things were re-checked and confirmed, and one BOM optimisation is recommended but not applied here (Board P's own page is the owner of that BOM):

1. Load re-check. Board P was margined against the 3.0 A contract cap. Board L actually draws ~410 mA (see Power budget). Every current-dependent number on Board P — Q1 conduction loss, JOUT contact loading, the XH derate — improves by roughly 7x against the original analysis. No part needs changing.

2. Clamp ceiling propagates downstream. D5 (SMAJ20A) clamps at ≤32.4 V worst case, and Q1 passes that transient straight to Board L when the switch is on. Board L's input-facing parts were selected against 32.4 V, not 15 V — see the driver input-rating decision.

3. The 5 V-only first-power-up rule is a hard bring-up gate, not advice. It is restated in Next Steps.

Net-connectivity table

Adopted verbatim from the power-section audit. Reproduced here so the architecture section is self-contained for schematic capture. Reference designators are Board P's own.

JOUT pin assignment (locked)

Board L's J2 must mirror this exactly. Both ends are the same part (C144397), joined by a 6-way XH harness.

ATT is wired to a GPIO purely because it is free — Board P already routes it to the connector, and an input pin costs nothing. Firmware does not act on it in v1.

Ratings, re-confirmed at Board L's real load

The two residual transient-only gaps (U1 VDD, Q1 VDS) are inherited unchanged from the ratings matrix. This architecture pass does not re-open them: they are surge-event-only, they were reasoned through against primary datasheets, and nothing about a lower steady-state load changes a clamp-event analysis.

One number this pass could not resolve

Lessons Carried From zudo-pd states that R14 (470 Ω from VBUS_IN to pin 18) passes "15 V/470 Ω ≈ 32 mA", inside the pin's 50 mA IDISUSB rating. Read as a continuous current that would be 0.48 W — more than 7% of the whole lamp's power budget, dissipated in a 0603 resistor rated 100 mW, which cannot be right. Read as the discharge-event current (pin 18 is high-impedance in its sense role and only sinks during discharge) it is ~0 W steady state, and the 50 mA figure is exactly what an event-current rating looks like.

This pass believes the second reading is correct — IDISUSB is named for discharge, and a 100 mW resistor in ST's own reference topology would not be specified to run at 4.8x its rating. But it could not confirm it from the datasheet text available here. The power budget therefore carries it as a flagged worst case (+0.48 W), and Next Steps makes measuring R14's steady-state drop an explicit bring-up item. Either way the design fits inside 45 W with large margin, so this does not block the build — but do not size R14's package from the optimistic reading without measuring it.

References

• Board P — USB-PD Front End — source of this circuit

• Worst-Case Ratings Matrix — per-part margin evidence

• Charger Compatibility — the 15 V-PDO purchase rule

• Lessons Carried From zudo-pd — CC topology, NVM trap, CPL rotation