Prototype Architecture — Overview

The locked prototype architecture for the lamp — two boards, a 24-LED warm-white array at 500mA, an AL8860 constant-current buck, an STM32G031 control MCU, and an EC11 knob mapped to brightness. Decisions, not options.

This section is the locked prototype architecture: the thing KiCad work starts from. Everything here is a decision with a recorded reason that traces back to the power and research sections. Where those pages enumerated options, this section picks one and says why — see Decisions for the chosen-vs-rejected record.

Nothing here is bench-confirmed

Board P's topology was never validated on working hardware (seeLessons Carried From zudo-pd), and Board L is a new design that has never existed as a PCB. This is a datasheet-grounded paper design. Treat the first build as the first real test, and follow the bring-up gates inNext Steps.

Headline numbers

Parameter	Locked value
Board count	2 — Board P (USB-PD front end) + Board L (driver, LEDs, control)
PD contract	15 V / 3 A (45 W cap)
System draw	~6.2 W, ~410 mA — 13.7% of the contract cap, 7.3x margin
LED array	24x SMD2835 warm white, 8 parallel strings of 3 series
CCT / CRI	3000 K (2800–3100 K bin), CRI Ra ≥ 80
Drive current	500 mA total, 62.5 mA per string
Light output	~700 lm typical, ≥620 lm worst-case bin
Driver	AL8860MP-13 constant-current buck, hysteretic, ~440 kHz
Logic rail	3.3 V from an AP63203 synchronous buck
MCU	STM32G031F8P6 (Cortex-M0+, 64 KB flash, TSSOP-20)
Knob	EC11 rotary encoder → base brightness
Dimming	Analog (RC-filtered 20 kHz PWM into the driver's CTRL pin) — no visible flicker by construction
Board L dissipation	~6.1 W spread over 24 LED sites + 8 ballast resistors — plain FR-4, no MCPCB

System block diagram

flowchart TD CHG["USB-C PD charger\n15V PDO required"] subgraph BP["Board P — USB-PD front end (existing spec)"] J1["J1 TYPE-C-31-M-17\nreceptacle"] U1["U1 STUSB4500QTR\nPD sink controller"] Q1["Q1 AO3401A\nload switch"] D5["D5 SMAJ20A\n20V standoff, 32.4V clamp"] J2P["J2/J3 pogo pads\nNVM I2C + debug"] JOUT["JOUT B6B-XH-A 6P"] J1 --> U1 U1 -->|"VBEN"| Q1 D5 --- U1 J2P --- U1 Q1 --> JOUT U1 -->|"ATT / PDOK"| JOUT end subgraph BL["Board L — driver + control + LED array"] J2L["J2 B6B-XH-A 6P"] F1["F1 PPTC 750mA/30V"] V15["15V rail\nD10 SMAJ20A + bulk caps"] U2["U2 AL8860MP-13\nCC buck, Rs=200mR"] ARR["LED array\n8 strings x 3s\n8x 33R ballast\n24x HL-AM-2835H421W"] U4["U4 AP63203WU-7\n3.3V synchronous buck"] V33["3.3V logic rail"] U3["U3 STM32G031F8P6\nCortex-M0+"] SW1["SW1 EC11 encoder\nquadrature A/B"] RC["R20 10k + R21 33k + C21 100n\nRC low-pass, 0 to 2.53V"] J3L["J3 SWD pads\nJ4 UART pads"] J2L --> F1 F1 --> V15 V15 --> U2 U2 -->|"L1 33uH + D11 SS26"| ARR ARR -->|"NTC RT1 10k"| U3 V15 --> U4 U4 --> V33 V33 --> U3 SW1 --> U3 U3 -->|"PA6 PWM 20kHz"| RC RC -->|"analog CTRL"| U2 J3L --- U3 J2L -->|"ATT / PDOK"| U3 end CHG -->|"USB-C cable"| J1 JOUT -->|"switched 15V x2, GND x2, ATT, PDOK"| J2L

Board split

Two boards, no LED daughterboard. Board P must be its own PCB (it is a reusable switched-15 V sink module, and it has to be bench-brought-up alone before anything is connected to it). Everything else lands on Board L.

The case for a third board — an LED module on aluminum MCPCB — was evaluated and rejected. The thermal budget page sets the plain-FR-4 ceiling at roughly 1 W per LED site; this design runs 0.19 W per site across 24 sites. That is squarely in that page's "many small sites, generous pour" regime, not the concentrated-COB regime that forces metal core. A third board would add a second interconnect carrying the driver's switching node over a cable — a real EMI cost — to solve a thermal problem this design does not have.

The split boundary is still designed in

The LED array is drawn as a self-contained block with a 4-net interface: LED_P(array anode rail), LED_N (common cathode = the driver's switching node), NTC_SENSE, and GND. If the later enclosure phase forces the emitters onto a separate plane from the knob, the array can be lifted onto a daughterboard across exactly those four nets without touching the rest of Board L. The reason it is not split now is the LED_Nswitching node: running a ~440 kHz, 15 V-swing node down a wire harness is an EMI problem that only pays for itself if the mechanics actually demand it.

Interfaces

Interface	Physical	Nets
Charger → Board P	USB-C receptacle (J1)	CC1, CC2, VBUS, GND
Board P → Board L	JST XH 6-pin harness, 2.5 mm pitch, both ends `B6B-XH-A(LF)(SN)`	1,2 = switched 15 V (paired); 3 = ATT; 4 = PDOK; 5,6 = GND (paired)
Board P programming	J2 pogo pads 1x4 (I2C NVM), J3 pogo pads 1x8 (debug)	SCL, SDA, GND
Board L programming	J3 pad group 1x5, 2.54 mm (SWD)	SWDIO, SWCLK, NRST, 3V3, GND
Board L debug	J4 pad group 1x3, 2.54 mm (UART)	PA2 TX, PA3 RX, GND
User control	EC11 rotary encoder, panel-mount bushing	A, B, common

The XH connector's per-contact current math is inherited unchanged from Board P's downstream interface: 3 A/contact nameplate, doubled contacts per rail. Against this design's actual 410 mA draw that is 14x derated margin per contact, not the 1.6x the connector was sized for against the 3 A contract cap. The doubling stays anyway — it costs nothing, it is already in Board P's spec, and it keeps the harness reusable if a brighter revision raises the current.

What the knob does

The knob sets base brightness, and nothing else. Speed and depth of the fire/wave modulation are firmware constants. The full reasoning is in Decisions; the short version is that a lamp knob that does not change brightness is a surprise, and the chosen EC11 SKU's push-button presence could not be confirmed from the parts DB, so a mode-cycling gesture cannot be relied on.

Where to go next

Page	Contents
Board P	Locked front-end spec, full net table, interface pin assignment
Board L	Driver/control/LED design, full pin-level net table, all component values with worked math
Final BOM	Every part, C-number, tier, stock, and the Extended-fee arithmetic
Decisions	Chosen vs rejected per slot, with reasons
Next Steps	The KiCad phase — bring-up order, footprint pipeline, risks