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Board P — USB-PD Front End

The USB-PD 15V/3A sink front end for this lamp — adapted from the zudo-pd project's reusable Board A core (STUSB4500 + USB-C receptacle + load switch + NVM/debug pads), audited against primary datasheets rather than copied verbatim.

Board P is this lamp's dedicated USB-PD processing board. It negotiates a 15 V/3 A USB-PD contract from a USB-C charger, load-switches it, and hands a clean switched 15 V rail (plus GND and two optional status flags) to whatever board consumes power downstream — the LED power stage and/or control board being researched in parallel as separate doc sections. The exact board split is locked by the prototype-architecture decision, not by this page.

The circuit below is adapted from the zudo-pd project's "Board A" — a small, reusable USB-PD 15 V sink module the zudo-pd project split out specifically so other projects could reuse it. This page is an audit, not a copy-paste: every LCSC part number was re-verified against the local JLCPCB parts database, and every rating claim was re-checked against the actual manufacturer datasheet rather than trusted from zudo-pd's prose. One part failed that check — see Worst-Case Ratings Matrix for the USB-C receptacle swap this audit made.

Note

This is a documentation-only deliverable, same as zudo-pd's own Board A page. No.kicad_sch / .kicad_pcb file exists for Board P yet — that is a later KiCad phase per the epic's scope boundaries. The net table below describes the circuit Board P's schematic should implement; reference designators (U1, Q1, J1, D5, R11–R20, C1/C2/C30/ C34/C35) are carried over from zudo-pd's Board A for continuity, not from an existing Board P schematic.

Purpose

  • Proven front-end topology. zudo-pd's single-board design failed USB-PD negotiation across four separate PCBA orders (v1–v4) before the front end was diagnosed, fixed on paper, and split into its own board. Board P inherits that post-fix topology directly, rather than re-deriving it from scratch.

  • Generic, reusable "switched 15 V sink" module. Nothing in this circuit is lamp-specific — it negotiates 15 V over USB-PD, switches it, and exposes GND plus two generic status flags. Any downstream board that just needs a switched 15 V rail can consume it.

  • NVM-programmable. The same board carries I2C pogo pads for writing the STUSB4500's PDO configuration — see Lessons Carried From zudo-pd for the factory-default 20 V trap this NVM step exists to close.

Block diagram

flowchart TD J1["J1 USB-C receptacle\nCC1/CC2 plain copper, no external Rd"] -->|"CC1 / CC2"| U1["U1 STUSB4500QTR\nPD sink controller"] J1 -->|"VBUS_IN"| U1 DB["R19 / R20 (0 ohm)\nCC1DB<->CC1, CC2DB<->CC2 bridges"] --- U1 RD["R17 / R18 5.1k ext Rd\nDNP (rework insurance only)"] -.-> J1 CCESD["D6 / D7 PESD24VS1UB\nDNP (enclosed/production builds only)"] -.-> U1 U1 -->|"VBUS_VS_DISCH via R14 470R"| P18["Pin-18 sense/discharge"] U1 -->|"VBEN (active-low OD)"| GATE["Q1 gate node\nR11 100k pull-up, R12 56k series, C35 100n softstart"] GATE --> Q1["Q1 AO3401A P-FET\nload switch"] D5["D5 SMAJ20A\nVBUS clamp"] --- U1 D5 --- J1 Q1 -->|"VBUS_OUT (switched 15V)"| JOUT["Downstream interface connector\nVBUS_OUT x2, GND x2, ATT, PDOK"] U1 -->|"ATT (open-drain)"| JOUT U1 -->|"PDOK (open-drain)"| JOUT J2["J2 pogo pads (1x4)\nNVM I2C programming"] --- U1 J3["J3 pogo pads (1x8)\ndebug: CC1DB CC2DB VREG_2V7 VBUS_IN GND ATT PDOK VBEN"] --- U1 JOUT -->|"switched 15V + GND"| DOWNSTREAM["Downstream board(s)\n(LED power stage / control — TBD by wave-3 architecture decision)"]

Net-connectivity table

Per the zudo-pd project's net-table + Mermaid convention (a "never ASCII-art schematics" documentation rule — connectivity is recorded as a table derived from netlist data, illustrated at block level by Mermaid). This table describes the target circuit for Board P's own future schematic; it is not yet exported from a KiCad netlist because that schematic does not exist yet.

NetConnected pins (Ref.Pin)Value/Note
VBUS_INJ1.A9 J1.B9 U1.VDD C1.2 C2.2 R14.1 R11.2 Q1.S J3.4 D5.cathodeReceptacle VBUS (5 V pre-contract, 15 V post-contract). U1.VDD direct (operating range 4.1–22 V, absolute max 28 V — see ratings matrix). C1 10 µF + C2 100 nF decoupling. D5 cathode = SMAJ20A VBUS clamp
CC1J1.A5 U1.CC1 R17.1(DNP) R19.2 D6.1(DNP)Connector CC1 to U1.CC1 is plain copper. R17 (5.1 kΩ external Rd) is DNP — see lessons for why. R19 (0 Ω, fitted) bridges CC1DB↔CC1. D6 = PESD24VS1UB, DNP
CC2J1.B5 U1.CC2 R18.1(DNP) R20.2 D7.1(DNP)Mirror of CC1
CC1DBU1.CC1DB R19.1 J3.1Dead-battery pin. R19 (0 Ω) bridges to CC1 net — restores ST's VBUS-only-sink reference topology (DS12499 §3.5)
CC2DBU1.CC2DB R20.1 J3.2Mirror; R20 bridges to CC2
VBUS_VS_DISCHU1.pin18 R14.2Pin-18 sense/discharge node. R14 470 Ω series from VBUS_IN
VBEN (VBUS_EN_SNK)U1.pin16 R12.1 J3.8Active-low open-drain. R12 56 kΩ series to the gate node
Net-(Q1-G)Q1.G R11.1 R12.2 C35.1Q1 gate. R11 100 kΩ pull-up to VBUS_IN (default OFF). C35 100 nF soft-start to GND (τ ≈ 56 kΩ × 100 nF ≈ 5.6 ms)
VBUS_OUTQ1.D R13.1 JOUT.1 JOUT.2Switched output of the load switch — the reusable "switched 15 V sink" rail, paired across two downstream connector pins for current sharing
Net-(U1-DISCH)U1.DISCH R13.2DISCH pin → R13 470 Ω → VBUS_OUT (system-side discharge)
VREG_2V7U1.VREG_2V7 C30.2 R15.2 R16.2 J3.32.7 V internal regulator / I2C pull-up rail. C30 decap
Net-(U1-VREG_1V2)U1.VREG_1V2 C34.11.2 V internal digital-core regulator. C34 decap
SCLU1.SCL R15.1 J2.1NVM programming clock. R15 4.7 kΩ pull-up to VREG_2V7
SDAU1.SDA R16.1 J2.2NVM programming data. R16 4.7 kΩ pull-up
ATTU1.ATTACH J3.6 JOUT.3ATTACH flag, open-drain active-low, no on-board pull-up
PDOKU1.POWER_OK2 J3.7 JOUT.4Asserts on a live PDO2/15 V contract, open-drain active-low, no on-board pull-up
GNDU1.GND U1.RESET U1.ADDR0 U1.ADDR1 U1.VSYS U1.EP J1.GND C1.1 C2.1 C30.1 C34.2 C35.2 R17.2(DNP) R18.2(DNP) J2.3 J3.5 D5.anode D6.2(DNP) D7.2(DNP) JOUT.5 JOUT.6Common ground. U1.RESET active-high, grounded = run. U1.ADDR0/1 → I2C address 0x28. U1.VSYS grounded (VDD-only supply). U1.EP = exposed thermal/electrical pad
Unused U1 pinsNC, POWER_OK3 (float), GPIO (float), A_B_SIDE (float), ALERT (float)Same disposition as zudo-pd's Board A
J2 pad 4J2.4Unconnected (NC)

Warning

No 5 V-class USB ESD array (e.g. a USBLC6-2SC6-family part) belongs anywhere on this board's VBUS path. See Lessons Carried From zudo-pd for why zudo-pd's early revisions failed exactly this way.

Component list, LCSC parts, and rough cost

All LCSC numbers below were independently re-verified via the local JLCPCB parts database (dated 2026-07-25) — not copied from zudo-pd's BOM page, which that project's own docs flag as having drifted. https://jlcpcb.com/partdetail/C{number} links are included for each. See Worst-Case Ratings Matrix for the per-part rating evidence and the one part this audit swapped out.

RefPartLCSCPackageRoleStock (DB 2026-07-25)
U1STUSB4500QTRC2678061QFN-24-EP (4×4)PD sink controller4,562
Q1AO3401AC347476SOT-23Load switch (P-FET)862,120
J1TYPE-C-31-M-17C2835406P SMD, right-angleUSB-C PD input — replaces zudo-pd's C456012, see ratings matrix33,876
D5SMAJ20AC571370 (alt C1973455)SMAVBUS TVS clamp3,770 (alt: 1 — essentially depleted, use primary)
C110 µF 50V X5RC135851206VDD bulk decouple1,877,266
C2100 nF 50V X7RC17110805VDD HF decouple17,509
C301 µF 50V X5RC158490603VREG_2V7 decouple5,979,916
C341 µF 50V X5RC158490603VREG_1V2 decouple5,979,916
C35100 nF 50V X7RC17110805Gate soft-start17,509
R11100 kΩC258030603Gate pull-up7,990,119
R1256 kΩC232060603Gate divider219,781
R13470 ΩC231790603DISCH resistor1,899,614
R14470 ΩC231790603Pin-18 series R1,899,614
R154.7 kΩC231620603I2C SCL pull-up7,433,362
R164.7 kΩC231620603I2C SDA pull-up7,433,362
R190 ΩC211890603CC1DB↔CC1 link (fitted)6,153,233
R200 ΩC211890603CC2DB↔CC2 link (fitted)6,153,233
J2Pogo pads, 1×4— (bare copper, no part)Custom SMDNVM I2C programming$0
J3Pogo pads, 1×8— (bare copper, no part)Custom SMDDebug pads$0
JOUTJST B6B-XH-A(LF)(SN)C144397THT, 2.5 mm pitchDownstream interface connector47,935

DNP (footprint only, not populated):

RefPartLCSCPackageNote
R17, R185.1 kΩC231860603External Rd, rework insurance only — never populate on a powered build
D6, D7PESD24VS1UBC85382SOD-523CC-line ESD, enclosed/production builds only

Downstream interface

Board P exposes exactly what a "switched 15 V sink module" needs to hand off: switched 15 V (paired, 2 pins), GND (paired, 2 pins), and two optional open-drain status flags — ATT (cable attached) and PDOK (live 15 V PD contract). This mirrors the interface contract zudo-pd's Board A uses toward its own downstream board, reusing the same connector choice (JST B6B-XH-A(LF)(SN), 6-pin, 2.5 mm pitch, 3 A/contact) for the same reasons: polarized/shrouded housing, genuine-JST stock at JLCPCB, and through-hole anchoring appropriate for a power connector.

Note

The exact downstream consumer (LED power stage, control board, or a single combined board) is not locked by this page — that split is the prototype-architecture decision's job. Nothing about Board P's interface assumes a particular downstream split: a consumer that ignores ATT/PDOK just gets switched 15 V, same as zudo-pd's own reuse guidance states.

Current-rating math (same method zudo-pd used for its A↔B interface): worst case is the PD contract cap of 3.0 A at 15 V. The XH connector is rated 3.0 A/contact; at an 80% continuous derate that is 2.4 A/contact. Two contacts per power rail give 4.8 A derated capacity against a 3.0 A load — each contact carries 1.5 A, 50% of nameplate, for a 1.6× derated margin (2.0× nameplate). GND uses the identical two-contact math.

Reuse guidance

  • Minimum wiring: connect the two VBUS_OUT pins and two GND pins to the consuming circuit. ATT/PDOK may be left unconnected — Board P negotiates and switches power autonomously.

  • NVM reconfiguration: the negotiated voltage/current live in the STUSB4500's NVM, not in the schematic — see Lessons Carried From zudo-pd for the programming procedure and its pitfalls.

  • Electrical limits to respect downstream: anything wired to VBUS_OUT must tolerate the D5 (SMAJ20A) clamp ceiling during a fault event, not just the nominal 15 V — see Worst-Case Ratings Matrix for the exact numbers and which parts have residual (accepted, transient-only) margin gaps against that ceiling.

References

  • The zudo-pd project's Board A design (STUSB4500-based reusable USB-PD 15 V sink core) — the direct source of this circuit, credited throughout this page.

  • Worst-Case Ratings Matrix — per-part datasheet-sourced rating verification, including the USB-C receptacle swap.

  • Charger Compatibility — why the front end uses an auto-negotiating certified controller instead of a resistor-strapped one.

  • Lessons Carried From zudo-pd — design rules, the NVM factory-default trap, JLCPCB CPL gotchas, and the standalone bring-up sequence.

Revision History

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